(This position includes requirements from multiple departments, and the specific requirements will vary depending on the department.)
Responsibilities
1. Design, develop, and verify RTL/digital circuits, including synthesis and simulation.
2. Engage in FPGA synthesis, verification, and emulator platform integration.
3. Develop and integrate SoC architecture and high-speed Serdes IO.
4. Perform system integration, ASIC/FPGA verification, and support mass production IC maintenance.
5. Enhance design robustness and verification environment, and support compliance testing for high-speed interfaces.
1. Proficient in ASIC design flow, including UPF, synthesis, STA, and DFT methodologies.
2. Experienced in ASIC/FPGA integration, ARM CPU architecture, and high-speed I/O protocols (PCIe, USB, DDR).
3. Skilled in Verilog/SystemVerilog RTL coding and familiar with scripting languages (TCL, Perl, shell scripts).
4. Knowledgeable in EDA tools (Design Compiler, PrimeTime, Conformal LEC) and advanced process nodes (28nm, 12nm).
5. Familiar with low-power design, SOC DFT implementation, and compliance testing for USB3.2, SATA, PCIe.
出差外派
不需出差
上班時段
日班
遠端工作
現場
上班地點
新北/新竹
休假制度
符合勞基法
可到職日
依面談為主
招募人數
1人
股票與獎金
無
工作經歷
3-5年
學歷要求
大學或同等學歷以上
語言要求
薪資待遇補充說明
固定或變動薪資因個人資歷或績效而異
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