1. Engage in physical design tasks.
2. Including floorplanning, power grid design, physical synthesis, clock tree synthesis, routing, and DRC/LVS leading to tapeout.
1. Proficient with EDA tools such as Synopsys ICC2 or FC, PrimeTime, Cadence Innovus, and Tempus.
2. Capable of executing the netlist-to-GDSII design flow, covering floorplanning, power grid development, clock tree synthesis, place and route, and physical verification.
3. Skilled in hierarchical implementation, low-power design methodologies, timing closure, IR drop analysis, and crosstalk analysis.
4. Experienced with scripting languages like TCL, Perl, and Python for design automation.
5. Experience in 55nm/40nm design is essential; familiarity with 28nm/16nm or smaller nodes is a plus.
6. Expertise in FinFet design is essential, and experience in whole chip integration is advantageous.
Expatriate
不需出差
Working Hours
日班
Remote Work
現場
Job Location
新北市
Holiday
符合勞基法
Onboard Day
依面談為主
Number of Vacancies
1人
Stock and Bonus
無
Experience Required
3-5年
Education Required
大學或同等學歷以上
Language Required
Additional Salary Information
固定或變動薪資因個人資歷或績效而異
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